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NCP3125
T J + T A ) P D @ R q JA
ambient temperature. The formula for calculating the
junction temperature with the package in free air is:
(eq. 35)
P D = Power dissipation of the IC
R q JA = Thermal resistance junction to ambient of
the regulator package
T A = Ambient temperature
T J = Junction temperature
As with any power design, proper laboratory testing
should be performed to ensure the design will dissipate the
required power under worst case operating conditions.
F SW = Switching frequency
F ESR = Output capacitor ESR zero frequency
If the criteria is not met, the compensation network may
not provide stability and the output power stage must be
modified.
Figure 23 shows a pseudo Type III transconductance error
amplifier.
ZIN
CF
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
IEA
R1
RF
maximum input voltage, maximum loading, and component
variations (i.e., worst case MOSFET R DS(on) ).
Compensation Network
CC
ZFB
CP
Gm
R2
To create a stable power supply, the compensation
network around the transconductance amplifier must be
used in conjunction with the PWM generator and the power
stage. Since the power stage design criteria is set by the
RC
VREF
F LC +
3
3.102 kHz +
application, the compensation network must correct the over
all system response to ensure stability. The output inductor
and capacitor of the power stage form a double pole at the
frequency as shown in Equation 36:
1
2 p L OUT C OUT
(eq. 36)
1
2 p 5.6 m H 470 m F
C OUT = Output capacitor
F LC = Double pole inductor and capacitor
frequency
L OUT = Output inductor value
The ESR of the output capacitor creates a “zero” at the
frequency as shown in Equation 37:
Figure 23. Pseudo Type III Transconductance Error
Amplifier
The compensation network consists of the internal OTA
and the impedance networks Z IN (R 1 , R 2 , R F , and C F ) and
external Z FB (R C , C C , and C P ). The compensation network
has to provide a closed loop transfer function with the
highest 0 dB crossing frequency to have fast response and
the highest gain in DC conditions to minimize the load
regulation issues. A stable control loop has a gain crossing
with ? 20 dB/decade slope and a phase margin greater than
45 ° . Include worst ? case component variations when
determining phase margin. To start the design, a resistor
value should be chosen for R 2 from which all other
components can be chosen. A good starting value is 10 k W .
The NCP3125 allows the output of the DC ? DC regulator
F ESR +
6.772 kHz +
2 p
2 p
1
CO ESR
1
0.050 m W
3
C OUT
470 m F
(eq. 37)
to be adjusted down to 0.8 V via an external resistor divider
network. The regulator will maintain 0.8 V at the feedback
pin. Thus, if a resistor divider circuit was placed across the
feedback pin to V OUT , the regulator will regulate the output
voltage proportional to the resistor divider network in order
F SW
F ESR t
CO ESR = Output capacitor ESR
C OUT = Output capacitor
F LC = Output capacitor ESR frequency
The two equations above define the bode plot that the
power stage has created or open loop response of the system.
The next step is to close the loop by considering the feedback
values. The closed loop crossover frequency should be
greater than the F LC and less than 1/5 of the switching
frequency, which would place the maximum crossover
frequency at 70 kHz. Further, the calculated F ESR frequency
should meet the following:
(eq. 38)
5
to maintain 0.8 V at the FB pin.
V OUT
R1
FB
R2
Figure 24. Feedback Resistor Divider
The relationship between the resistor divider network
above and the output voltage is shown in Equation 39:
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